WHOLE_DRAFTER_FMAX_CENSUS_20260923
◐Running
At 66 MHz the worst routed paths are 14.47 ns (attention combine), 14.22 ns (G8 fp32 adder), 13.27 ns (array broadcast). All three are 78-94% route. Full census
Census pending (jobs queued on box1 and the laptop). Known so far: the three worst paths each need ~4.3-4.9 ns cut to close 100 MHz. Each has a named RTL site and a fix that costs a few cycles per pass.
HEAD_SEAM256_KVSKIP_20260924
◐Running
Seam export per child 26,434 → 10,754 (256 b) → 2,501 cycles (256 b + page bursts) in the unit gate; KV-only G5 426 cycles vs 750+84·ctx; full-HEAD byte identit
Both levers are byte-exact in every gate that has finished. The 256-bit port ALONE removes only ~44% of the silicon export time, because the 1,216 per-cell B round trips dominate; page-capped bursts (mode 2) reach the model's 40 µs, but they are in the risk class of R2 (the 0x1190 accept collapse suspect), so mode 1 is the first image candidate. The KV-only skip makes a KV-only row's attention ctx-independent (426 cycles in the drafter).
ARRAY_DUALCLK_20260923
◐Running
Bit-exact; HEAD item 1.77x fewer 66 MHz cycles in full-drafter xsim; array harness routes 133/66 with CDC clean; full-HEAD image 0xE4B711CD building
Running the array alone at exactly 2x the drafter clock, fed by a per-die BRAM activation cache, is bit-exact and cuts the HEAD item from 33,010 to 18,610 clk in the real drafter. The array-only harness closes 133.3/66.7 MHz on both clocks with report_cdc clean. Whether the full HEAD image closes and how it performs on silicon is pending.
GPU_WIDTH_DEPTH_ACCEPT_GRID_20260924
◐Running
Width 3 keeps 95.5% (mt_bench) / 97.8% (humaneval) of width 8's accept at depth 2; GPU bs2 = 453 tok/s mt d2 w8
Narrow trees lose less accept than the pair model assumed (width 3 keeps ~95-98% at depth 2); part of that loss is just the 13-token verify budget. The GPU bar rises ~1.4x at batch 2. Deep cells still landing.
G4_EMBFOLD_INTEGRATION_20260924
◐Running
Table builder bit-exact on 2,039 RTL-oracle keys; max|P| = 2^28.2 over all 128,256 tokens so 4 B entries fit; fetch engine unit-gated; full-drafter gate queued
The P table (9.46 GB, 9 HBM PCs) is built and matches the RTL integer model exactly. The HBM fetch engine passes its unit gate with a working RED. The host path passes its mock gate. The full-drafter gate is still queued, so no HEAD-level claim is made yet.
ENGINE_SPLIT_PAIR_STEP3_20260923
◐Running
Both cards run a full md=2 tree end to end over 2x hop_link with 0 link errors; bit-exact verdict pending
The two-card protocol works end to end (24 items, 72-node tree, 0 CRC/seq/overflow). Hop 3 must carry GLM + G11 (211 wire cycles). The GEMV item FIFO must hold K_F=8. The full-data bit-exact gate and the RED arms are still running.
LAPTOP_BUILD_HOST_AND_D6_20260924
◐Running
Laptop verified as a full-PDI build host (license, AMC FW, dry STEP0-3); D6 (LANES 256 + RET_SER) queued, no fit numbers yet
The laptop now reproduces the VM build flow's inputs byte for byte and passes every pre-build check. D6 has not been admitted yet, so no D6 placement, SLL or timing number exists; D3 (LANES 128) is the comparator.
TREE_WIDTH_PAIR_20260924
◐Running
Tree width is now a TAIL register (0x1CC, 1..8, reset 8); the HEAD needs no change; unit + RED gates GREEN; TAIL CF building
Width 3 needs ONE new image: the TAIL. On the HEAD the width is inert (level/branch come from the host header; the KV lane slot has no width term). The register is latched per tree, so it can change between trees on a PERSIST image. A barrier/width mismatch ends in a bounded timeout, not a silent hang. No tok/s is measured yet.
PAIR_HOST_OVERHEAD_20260923 + HOST_OVERLAP_IMPL_20260924
◐Running
HOSTFAST=1: 97.23 → 101.86 tok/s (+4.8%) at accept 2.22, 50/50 outputs identical; overlap levers mock-proven, silicon A/B pending
Five host cuts (catch-up overlap, telemetry and logging off, one SoA read per tree, relay read-back after the doorbell) are measured on silicon: +4.8% tok/s with identical outputs in 35 runs. The HEAD is never idle inside level 1; what remains is GPU verify, the level-0 barrier, the level-1 drain, and ~2.2 ms/step of glue. The worker-GIL fix and the early tree launch are proven only on the mock pair.
ARRAY_SYSTOLIC_LUTGEMM_20260923
◐Running
LUT-GEMM g=2: bit-exact, 0 cycles, −39.6% array LUT; systolic feed: bit-exact but no clock gain at L128 (174 vs 177 MHz)
Adopt the LUT-GEMM (g=2) lane: exact, cycle-neutral, −138K LUT at LANES 128. Do not adopt the systolic activation chain for clock at LANES 128. Two routes (A2+B L128, L256 systolic vs broadcast) are queued, not run.
ENGINE_SPLIT_STATE_STEP2_20260923
✓Done
State card bit-exact vs single card: 7,414 items / 0 mismatches; GEMV card 24/24; hop_link 40,800 hops exact
Both halves of the engine split reproduce the single-card drafter bit-for-bit in xsim (md=2, ctx 16, OSPREY 32×96), RED arms fire, and the link transport delivers every hop exactly under back-pressure. No synthesis, timing or silicon yet; the pair speed-up is still a model.
SIBLING_W_ON_GEMV_CARD_20260923
◐Running
W=4 array placed with 821/516 SLL (August W=8 needed 23,907); W=8 bit-exact in xsim; W=8 at 128 lanes is now blocked by AREA, not wire. W=8 NOT yet placed.
Per-die activation replicas + a W-wide serialised return remove the August inter-die-wire wall for the array (measured at W=4, 821 SLL). The new wall is die area: 2,038 LUT per lane-column measured, so W=8 x 128 lanes is ~157% of the routable LUT budget (derived). Once the GEMV sweep is batched, the state card's per-child G12/TREE/G8 tail dominates a level.
ARCH_PAGE_20260923
✓Done
Weights sit with every lane; 123 of 128 lanes get activations from another die
On the placed HEAD 0x11C9 every GEMV lane's weight bank is on its own die, but all three activation broadcast replicas and every result consumer sit in SLR1, so most GEMV traffic crosses a die boundary; attention fills 40,205 of SLR1's 98,416 drafter SLICE and the TAIL carries an unused copy of it.
ARRAY_POC_20260923
◐Running
M2: routed 166 MHz (+0.041 ns), 14,316 HEAD cycles ⇒ ≈5.4× array-only
M2 (LANES 256 + E3 packed-DSP lane + locality + RET_SER + TILE_PIPE + FOLD) is bit-exact, closes 166 MHz and needs 2.16× fewer cycles; the drafter around it was not run at 166 MHz. M3 P&R pending.
ARRAY_POC_20260923
◐Running
M2: routed 166 MHz (+0.041 ns), 14,316 HEAD cycles ⇒ ≈5.4× array-only
M2 (LANES 256 + E3 packed-DSP lane + locality + RET_SER + TILE_PIPE + FOLD) is bit-exact, closes 166 MHz and needs 2.16× fewer cycles; the drafter around it was not run at 166 MHz. M3 P&R pending.
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