L1 locality floorplan — group g of lanes, its broadcast replica, the boot replica, the reset replica and its return registers all in SLR g (IDX_GRP=1, RST_PIPE=2, soft pblocks). Goal: raise fmax, cut SLL.
L2 widen — LANES=256 (L2a) and K_PAR=32 with a new URAM bank (L2b).
L3 DSP MACs — DOT_DSP systolic DSP58 chains (prior art) and E3, the adder-study cross-lane packed DSP lane (two lanes per DSP multiplier).
L4 keep busy — TILE_PIPE=1: issue the next tile on ready, two accumulator banks.
L5 shortlist G12 — 256 tiles (FR-Spec 32K) instead of 1,002 (cycles only).
RET_SER (R=8/16) serialises the result return to cut wire; PIPE_FOLD pipelines the per-group scale fold.

Merges: M1 = L256 + L1 + RET_SER + TILE_PIPE + FOLD with the CSA lane; M2 = M1 with the E3 lane; M3 = M2 × K_PAR 32 on a mixed E3/F lane.

Method. (1) A/B xsim: DUT_A = the unmodified array, DUT_B = the variant, same matrix through each DUT's own boot port, random activations, every stage_sel exercised; each lever has a RED arm with a planted defect that must FAIL. (2) Cycle census in xsim with a minimal synchronous caller. (3) OOC synth → opt → place → phys_opt → route, then the same routed netlist re-timed at 66/100/133/166/200 MHz.

00Four-line snapshot

01Motivation

02Proposal

03Architecture

04Simulation results

05Synthesis & implementation results

06Conclusions

07Evidence