Put u_array on ap_clk_fast, which is exactly twice ap_clk and comes from the same MMCM. The slow seams deliver 2 activation chunks per 66 MHz cycle and a 2x array needs 4, so a cache is unavoidable. Each group of lanes (one per die) gets a local BRAM cache, read at that group's own lane index with the same two-register alignment the seam path has. The bridge fills it once per stage through the existing seam read ports; G7g and G7u share one fill.

slow→fast: start, boot writes, fill writes are slow-registered and qualified with first_half = tick_s ^ tick_f (one fast edge each).
fast→slow: done toggles in the fast domain; the slow side registers done and captures the results in the same edge.
EARLY_START launches the first tile mid-fill at the derived bound ceil((np+3)/2) slow cycles.

Gates: an xsim A/B against the unmodified array on all six stage_sels with real-weight-like stimulus and five RED arms; a cycle census over the real HEAD tile counts; a routed dual-clock harness with report_cdc on the routed netlist; and a full-HEAD byte-identical gate (29 exported seam items vs the C8 source).

00Four-line snapshot

01Motivation

02Proposal

03Architecture

04Simulation results

05Synthesis & implementation results

06Conclusions

07Evidence